Cognitive Reconfigurable Embedded Systems Lab
Tsung-Han Yu (S’10) received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, University of California, Los Angeles. His research is focused on digital integrated circuits and architectures for communication signal processing. Now he is working on development of algorithm and circuit architecture on wideband spectrum sensing for cognitive radios.
- Ph.D., Electrical Engineering, University of California, Los Angeles, CA, USA (In Progress)
- M.S., Graduate Institude of Electronic Engineering, National Taiwan University, Taiwan, 2007
- B.E., Electrical Engineering, National Taiwan University, Taiwan, 2005
Graduate Student Researcher, EE, UCLA
- Physical layer design of cognitive radio wideband spectrum sensing with presence of adjacent-band strong interferers.
- Cognitive radio wideband spectrum sensing algorithm using multitap windowed power detection and threshold adaptation.
- A wideband spectrum-sensing testbed with adaptive detection threshold and sensing time.
- A 7.4mW 200MS/s spectrum-sensing processor for cognitive radios.
- An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensing.
Graduate Student Researcher, EE, NTU
- Design and implementation of a baseband receiver for DVB-T/H standard.
3GPP-LTE Compliant 8×8 MIMO Decoder
|Technology||TSMC 65nm CMOS|
|Core VDD||0.4 – 1.0 Volt|
|Frequency||1.25 – 20 MHz|
|Gate Count||2.95M (NAND2 Eqvl.)|
|Core Size||2.39mm x 1.40mm (3.35mm^2)|
|Power||13.8 mW (5.8 mW for LTE)|
Wideband Spectrum Sensing Processor
|Technology||TSMC 65nm CMOS|
|Core VDD||0.7 – 1.0 Volt|
|Gate Count||1.46M (NAND2 Eqvl.)|
|Core Size||1.44mm x 1.14mm (1.64mm^2)|
- T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, “A 7.4 mW 200 MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios,” accepted by IEEE Journal of Solid-State Circuits (JSSC).
- C.-H. Yang, T.-H. Yu, D. Čabrić, and D. Marković, “Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example,” IEEE Journal of Solid-State Circuits (JSSC), to appear, Mar. 2012.
- T.-H. Yu, O. Sekkat, S. Rodriguez-Parera, D. Marković, and D. Čabrić, “A Wideband Spectrum-Sensing Processor with Adaptive Detection Threshold and Sensing Time,” IEEE Trans. on Circuit & System I (TCAS-I), vol. 58, no. 11, pp. 2765-2775, Nov. 2011.
- T.-H. Yu, C.-H. Yang, D. Marković, and D. Čabrić, “An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing” IEEE Global Telecommunications Conference (GLOBELCOM’11), Dec. 2011, pp. 1-6.
- T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, “A 7.4mW 200MS/s Spectrum-Sensing Digital Baseband Processor for Cognitive Radios,” IEEE Int. Symposium on VLSI Circuits (VLSI’11), Jun. 2011, pp. 254-255.
- C.-H. Yang, T.-H. Yu, and D. Marković, “A 5.8mW 3GPP-LTE Compliant 8×8 MIMO Sphere Decoder Chip with Soft-Outputs,” in Proc. IEEE Int. Symposium on VLSI Circuits (VLSI’10), Jun. 2010, pp. 209-210.
- T.-H. Yu, S. Rodriguez-Parera, D. Marković, and D. Čabrić, “Cognitive Radio Wideband Spectrum Sensing Using Multitap Windowing and Power Detection with Threshold Adaptation,” in Proc. IEEE Int. Conference on Communications (ICC’10), May 2010, pp. 1-6.
- I.-W. Lai, T.-H. Yu, T.-D. Chiueh, “Low-Complexity Adaptive Channel Estimation for OFDM System in Fast-Fading Channel,” in Proc. IEEE Int. Symposium on Circuit & System (ISCAS’09), May 2009, pp. 685-688.
- T.-H. Yu, I.-W. Lai, T.-D. Chiueh, “Design of a DVB-T/H Compliant Baseband Receiver,” in Proc. IEEE Int. Symposium on VLSI Design, Automation and Test (VLSI-DAT’08), Apr. 2008, pp. 279-282.
- Chancellor’s Prize Summer Mentorship, 2010 Summer, UCLA
- Chancellor’s Prize Summer Mentorship, 2009 Summer, UCLA
- Fellowship, 2008 Academic Year, UCLA
- Presidential Award, 2002 Academic Year, NTU