Cognitive Radio Testbeds
The UCLA CORES lab is equipped with several Cognitive Radio testbeds. These hardware/software platforms are used in an array of practical investigations ranging from hardware implementation and verification of novel algorithms to performance evaluations of current Cognitive Radio techniques. Using a rapid prototyping environment based on MATLAB/Simulink/SystemGenerator and Software Defined Radio strategies, our lab is able to quickly and effectively translate algorithmic ideas into real hardware that we leverage to further advance various dynamic spectrum access techniques.
Current Research Using CR Testbeds
- Low Complexity Modulation Classification for PU Identification
- Reliable Wideband Spectrum Sensing under Strong Interference Environments in Cognitive Radios
- Cyclostationary-Based Low Complexity Wideband Spectrum Sensing using Compressive Sampling
BEE2 and CR FrontEnd Platform
The Berkeley Emulation Engine along with several Radio Front Ends allow us to experiment with sensing algorithms and to demonstrate a working prototype of an indoor Cognitive Radio network. The BEE2, a multi-FPGA emulation engine developed at the University of California Berkeley Wireless Reasearch Center (BWRC), is capable of connecting to 18 radio front-ends. The testbed will is used to experiment with various baseband sensing algorithms, cooperative sensing schemes, as well as Primary User identification techniques such as localization and modulation classification.
A paper describing this prototyping platform can be found here: PDF
A testbed for Cognitive Radios must display the following features:
- Ability to support multiple radios which can serve as Primary or secondary users.
- Ability for PHY/MAC layer adaptation and fast information exchange between multiple radios for sensing and cooperation.
- Ability to perform rapid prototyping in order to experiment with different sensing algorithms.
Figure 1 shows an abstract diagram of the emulation platform. To implement multiple radios, the emulation platform must provide plenty of parallelism and mechanisms to connect to multiple frontends. Further more, the latency to exchange information between the various radios should be small.
The BEE2 platform
The Berkeley Emulation Engine (BEE2), is a generic, multi-purpose, FPGA based, emulation platform for computationally intensive applications. Each BEE2 can connect to 18 frontend boards via multi-gigabit interfaces.
The BEE2 consists of 5 Vertex-2 Pro 70 FPGAs. Each FPGA embeds a PowerPC 405 core which minimizes the latency between the microprocessor and reconfigurable logic. These 5 FPGAs form a single Compute Module. Each FPGA can be connected to 4 GBytes of memory with a raw memory throughput of 12.8Gps. Four FPGAs are used for computation and one for control as shown in Figure 2. Adjacent FPGAs are connected via onboard low-voltage 40Gbps (LVC-MOS) parallel interfaces. All computation FPGAs are connected to the control FPGA via 20Gbps links. These high bandwidth, low latency links allow the five FPGA to form a virtual FPGA of five times the capacity.
These FPGAs can connect to the external world using serial Multi-Gigabit (MGT) interfaces. Four MGTs are channel bonded to form a physical into a physical Infiniband 4X (IB4X) electrical connector, to form a 10 Gps full duplex interface. There are a total of 18 IB4X connectors per board. The Infiniband connectors allow the BEE2 Compute module to connect to an Infiniband switch which enables multiple BEE2 Compute models to communicate and exchange data. Figure 3 shows a picture of the BEE2 board.
Each BEE2 board supports one 100 Base-T Ethernet which is available on the control FPGA. The Power PC of the control FPGA can run Linux and a full IP protocol stack. The board also contains USB and JTAG interfaces along with provision for a flash card. The 100 Base-T interface allow remote management and control.
The BEE2 can be programmed using Matlab/Simulink from Mathworks coupled with the Xilinx system generator. The tool chain is augmented with BWRC developed automation tools for mapping high level block diagrams and state machine specifications to FPGA configurations. A set of parameterized library blocks have been developed for communications, control operators, memory interfaces and I/O modules.
Modular Front End System
The Front-end system has been designed in a modular fashion. The Analog/baseband board contains the filters, ADC/DAC chips and a Xilinx Vertex-II Pro FPGA. Digital-to-analog conversion is performed by a 14-bit DAC running up to 128MHz, while analog-to-digital conversion is performed by a 12-bit ADC running up to 64MHz. The FPGA performs data processing and control, and supports 4 optical 1.25 Gb/s links for transmitting and receiving data to/from BEE2. The optical link provides good analog signal isolation from digital noise sources and allows the frontend to be moved up to a third of a mile from BEE2 for wide range wireless experimentation. A separate RF modem module connects to the baseband board. The current RF modem module is capable of up/down converting 20MHz RF bandwidth at 2.4 GHz. The RF frequency is fully programmable in the entire 80MHz ISM band. A block diagram of a single RF modem is shown in Figure 4, while Figure 5 shows the RF and baseband boards.
Scalability is achieved through parallel RF modem modules being provided with a common RF reference and clock signals. Two configurations are supported by this architecture:
- All front-ends operate at the same radio frequency (The radios need to operate in Time Division Duplex (TDD) mode in a single 20MHz band).
- Groups of 4 or more antennas operate indifferent bands (The radios operate in Frequency Division Duplex (FDD) mode and occupy the entire 80MHz band).
Cognitive Radio setup
Since each BEE2 Compute board allows connection to 18 Front-ends, we can split the 18 interfaces between Primary and Secondary users. This will enable us to construct scenarios with multiple Primary users exhibiting different channel use patterns. Primary user traffic pattern can be controlled via the BEE2. Performance of energy and cyclostationary feature detectors can be characterized as a function of input SNR, sensing time, and modulation types. The on-board BEE2 implementation of various cooperation schemes will allow us real-time experimentation, even in dynamic Primary user traffic patterns. In addition, the optical links from BEE2 to front-end boards that reach 1/3 mile, facilitate experimentation in different shadowing and multipath environments. For the distributed detection of Primary users, protocols for the exchange of control information are necessary. Since a CR system does not provide a priori communication, a dedicated control channel must be used to exchange control information. The protocols used to implement these control channels are an integral part of the testbed.
USRP2 and GNURadio Platform
A set of USRP2s shown in Fig. 6 augment the CR front-ends for rapid prototyping and testing of algorithms. Using the open-source GNURadio stack, these software-defined front-ends allow for very flexible implementations of CR algorithms.
The USRP2 has the following specifications:
- Gigabit Ethernet interface
- 25 MHz of instantaneous RF bandwidth
- Xilinx Spartan 3-2000 FPGA
- Dual 100 MHz 14-bit ADCs
- Dual 400 MHz 16-bit DACs
- Locking to an external 10 MHz reference
- PPS (pulse per second) input
- Configuration stored on standard SD cards
- Standalone operation
- The ability to lock multiple systems together for MIMO